65nm CMOS op amp design (2016)


This design was completed as part of a midterm project for 6.775, MIT’s graduate level CMOS analog IC design class. The high level goal was to design an operational amplifier in 65nm CMOS technology, using Cadence Virtuoso design tools. The final report and full design and test details can be found here.

A summary of design performance specifications compared to this design’s performance can be found below.



The design was implemented as a 2-stage op amp, in a folded cascode input stage followed by a common source stage. This combination allowed for optima gain performance with the constraining power supply requirements, while still meeting phase margin and output swing requirements. A single ideal current source was provided for biasing purposes. Schematic details are found below.