250nm BiCMOS 1.8GHz RF Receiver (2016)


This design was completed as part of a final project for 6.776, MIT’s graduate level RF Integrated Circuit design class. The goal of the project was to design a 1.8V, 1.8GHz receiver (Low-noise Amplifier, Local Oscillator, Mixer) using IBM’s BICMOS6HP process. All design work was done using Cadence IC toolflow and SpectreRF for simulation. Final design report and details can be found here.

A summary of high-level product performance specifications and this design’s performance details can be found below.



Below is the high level schematic with testbench, including bondwire parasitics and port symbols for S parameter, noise and harmonic balance measurements.



The LNA was implemented using a Cascode topology for minimum area and low power consumption. In addition the single stage allows for maximum stability. The LNA was designed using inductive degeneration based on the widely documented Simultaneous Noise and Impedance Matching (SNIM) technique. LNA schematic below.


The LO was based on a cross-coupled topology. Based on design specifications, tunability was sacrificed in favor of low phase noise arising from the MOS capacitor. In addition, an LC low-pass network on the bias network drastically improves phase noise.



The mixer was based on the single-balanced Gilbert topology consisting of a common source transconductance stage driven by RF input, and a switching stage driven by the LO input. A differential NMOS source follower stage on the output allows for driving the low-impedance 50-ohm load. Mixer schematic below.


For full details including design methodology and test results please see final report above.